SMT-Based Bounded Model Checking of Fixed-Point Digital Controllers

Digital controllers have several advantages with respect to their flexibility and design's simplicity. However, they are subject to problems that are not faced by analog controllers. In particular, these problems are related to the finite word-length implementation that might lead to overflows, limit cycles, and time constraints in fixed-point processors. This paper proposes a new method to detect design's errors in digital controllers using a state-of-the art bounded model checker based on satisfiability modulo theories. The experiments with digital controllers for a ball and beam plant demonstrate that the proposed method can be very effective in finding errors in digital controllers than other existing approaches based on traditional simulations tools

Towards Global Neural Network Abstractions with Locally-Exact Reconstruction

Neural networks are a powerful class of non-linear functions. However, their black-box nature makes it difficult to explain their behaviour and certify their safety. Abstraction techniques address this challenge by transforming the neural network into a simpler, over-approximated function. Unfortunately, existing abstraction techniques are slack, which limits their applicability to small local regions of the input domain. In this paper, we propose Global Interval Neural Network Abstractions with Center-Exact Reconstruction (GINNACER). Our novel abstraction technique produces sound over-approximation bounds over the whole input domain while guaranteeing exact reconstructions for any given local input. Our experiments show that GINNACER is several orders of magnitude tighter than state-of-the-art global abstraction techniques, while being competitive with local ones.Comment: Under submission to the Neural Networks Journal (revised version). Sections 2, 4.7, 5.4, Appendix A and B have been adde

Passivation-based control reconfiguration with virtual actuators

This paper presents a novel approach for designing reconfiguration blocks for fault hiding of linear systems subject to actuator faults based on the passivity/dissipativity theory. For this purpose, the concept of passivation block is used to design virtual actuators (VAs) which guarantee that the faulty plant achieves the desired passivity indices and consequently the stability. Linear matrix inequalities (LMI)-based conditions are provided for designing the proposed VAs for ensuring the stability recovery for linear systems. Finally, a numerical example is used for assessing the proposed approach.Peer ReviewedPostprint (published version

Sound and Automated Synthesis of Digital Stabilizing Controllers for Continuous Plants

Modern control is implemented with digital microcontrollers, embedded within a dynamical plant that represents physical components. We present a new algorithm based on counter-example guided inductive synthesis that automates the design of digital controllers that are correct by construction. The synthesis result is sound with respect to the complete range of approximations, including time discretization, quantization effects, and finite-precision arithmetic and its rounding errors. We have implemented our new algorithm in a tool called DSSynth, and are able to automatically generate stable controllers for a set of intricate plant models taken from the literature within minutes.Comment: 10 page

Counterexample Guided Inductive Optimization Applied to Mobile Robots Path Planning (Extended Version)

We describe and evaluate a novel optimization-based off-line path planning algorithm for mobile robots based on the Counterexample-Guided Inductive Optimization (CEGIO) technique. CEGIO iteratively employs counterexamples generated from Boolean Satisfiability (SAT) and Satisfiability Modulo Theories (SMT) solvers, in order to guide the optimization process and to ensure global optimization. This paper marks the first application of CEGIO for planning mobile robot path. In particular, CEGIO has been successfully applied to obtain optimal two-dimensional paths for autonomous mobile robots using off-the-shelf SAT and SMT solvers.Comment: 7 pages, 14rd Latin American Robotics Symposium (LARS'2017

Data-driven prognostics based on evolving fuzzy degradation models for power semiconductor devices

The increasing application of power converter systems based on semiconductor devices such as Insulated-Gate Bipolar Transistors (IGBTs) has motivated the investigation of strategies for their prognostics and health management. However, physicsbased degradation modelling for semiconductors is usually complex and depends on uncertain parameters, which motivates the use of data-driven approaches. This paper addresses the problem of data-driven prognostics of IGBTs based on evolving fuzzy models learned from degradation data streams. The model depends on two classes of degradation features: one group of features that are very sensitive to the degradation stages is used as a premise variable of the fuzzy model, and another group that provides good trendability and monotonicity is used for the auto-regressive consequent of the fuzzy model for degradation prediction. This strategy allows obtaining interpretable degradation models, which are improved when more degradation data is obtained from the Unit Under Test (UUT) in real time. Furthermore, the fuzzy-based Remaining Useful Life (RUL) prediction is equipped with an uncertainty quantification mechanism to better aid decisionmakers. The proposed approach is then used for the RUL prediction considering an accelerated aging IGBT dataset from the NASA Ames Research Center.Postprint (published version

Descarte correto de pilhas e baterias: proposta de educação ambiental para escola estadual maria das dores brasil, boa vista, Roraima.

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Verification of Magnitude and Phase Responses in Fixed-Point Digital Filters

In the digital signal processing (DSP) area, one of the most important tasks is digital filter design. Currently, this procedure is performed with the aid of computational tools, which generally assume filter coefficients represented with floating-point arithmetic. Nonetheless, during the implementation phase, which is often done in digital signal processors or field programmable gate arrays, the representation of the obtained coefficients can be carried out through integer or fixed-point arithmetic, which often results in unexpected behavior or even unstable filters. The present work addresses this issue and proposes a verification methodology based on the digital-system verifier (DSVerifier), with the goal of checking fixed-point digital filters w.r.t. implementation aspects. In particular, DSVerifier checks whether the number of bits used in coefficient representation will result in a filter with the same features specified during the design phase. Experimental results show that errors regarding frequency response and overflow are likely to be identified with the proposed methodology, which thus improves overall system's reliability